1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus and a multi-chip package having the same, and more particularly, to a semiconductor memory apparatus which can control pads on both edges or one edge and a multi-chip package having the same.
2. Related Art
In general, as sizes of semiconductor packages gradually decrease due to the miniaturization of electronic appliances, such as portable electronics appliance, and trends toward light, thin, compact, and miniaturized designs increase, as well as demands for multi-functionality, requirements are made to decrease the thickness of the semiconductor package. Accordingly, a semiconductor package includes at least two semiconductor chips having the same functionality are stacked to increase capacity to at least two times. This stacked chip semiconductor package is commonly called a multi-chip package (MCP).
In the MCP, since a plurality of semiconductor chips can be provided in one package, an overall size of the package can be significantly reduced. However, when manufacturing the MCP, in order to prevent the bonding wires connected to the semiconductor chips from being damaged, support members, such as spacers, should be formed between the stacked semiconductor chips. Accordingly, the lengths of the bonding wires of the semiconductor chips are increased, wherein stability of the bonding wires deteriorates. In addition, the routing of signals through the bonding wires is problematic due to the increased lengthens of the bonding wires.
In addition, since address pads and command pads are located along one edge of the semiconductor chips and data input and output pads and power pads are located along another edge of the semiconductor chips, the pads on both edges must be employed for the operation of a semiconductor memory apparatus. Accordingly, during packaging processes, bonding wires must be formed on both edges to supply signals to the semiconductor memory apparatus.